1. Field of the Invention
The present invention relates to storage cells in memory arrays, and in particular, to storage cells operating with low power supply voltages.
2. Description of the Related Art
Dynamic random access memories (DRAMs) and static random access memories (SRAMs) typically include a number of storage cells that are organized in arrays having a plurality of rows and columns. In both DRAMs and SRAMs, a word line is associated with each row in the array. In DRAMs, one bit line is associated with each column in the array. With SRAMs, differential bit lines are associated with each column in the array. The reading or writing of a particular cell or row of cells in both DRAMs and SRAMs is performed using decoders, sense amplifiers, multiplexer circuits, write drivers, etc., in a well known manner, and is therefore not explained in greater detail herein.
A DRAM storage cell includes a pass transistor and a storage capacitor having a storage plate and a ground plate. The gate of the pass transistor of the cell is coupled to the word line associated with the row containing the cell. The source of the pass transistor is coupled to the storage plate of the capacitor and the drain is coupled to the bit line associated with the column containing the cell. When the cell is not being accessed (standby mode), the word line associated with the cell is typically held at VSS (e.g. 0.0 volts). To access the cell, the word line is driven high to VDD (e.g. 3.3 or 5.0 volts), causing the pass transistor to turn on. The pass transistor turns on when its gate potential (i.e., the word line) exceeds the threshold voltage V.sub.TH (e.g. 0.7 volts) of the transistor. During a write operation, the data present on the bit line is passed through the pass transistor, and is stored on the charge plate of the capacitor. Alternatively, during a read operation, the charge stored on the charge plate is "dumped" onto the bit line, and is then sensed to determine its value.
An SRAM storage cell typically includes two pass transistors and two inverters each having its output coupled to the other's input. The gates of the pass transistors are coupled to the word line associated with the row containing the cell. The source of the first pass transistor is coupled to the output of the first inverter and the input of the second inverter. The source of the second pass transistor is coupled to the output of the second inverter and the input of the first inverter. The drain of the first pass transistor is coupled to a first bit line associated with the column containing the cell, and the drain of the second pass transistor is coupled to a second bit line, or a "bit line bar", associated with the column. The operation of an SRAM storage cell is similar to a DRAM, except that the SRAM stores one charge on the output of one inverter and the complement of that charge on the output of the other inverter. During a write operation, the data present on the bit line is passed through the first pass transistor and is stored on the output of the first inverter, and the data present on the bit line bar is passed through the second pass transistor and is stored on the output of the second inverter. During a read operation, the logic levels stored on the outputs of the inverters are coupled onto the respective bit lines and sensed. Because inverters, rather than a capacitor, are used to maintain the stored charges, the SRAM is capable of maintaining the stored data for long periods of time without having to be electrically refreshed like the DRAM.
In prior art DRAM and SRAM storage cells, it is common to apply a negative substrate bias potential V.sub.sb to the pass transistor. The negative substrate bias potential V.sub.sb maintains the pass transistor in a "hard" off state, thereby reducing the loss of charge on the storage capacitor due to leakage through the pass transistor. The back bias potential V.sub.sb has the effect of shifting the V.sub.TH of the pass transistor, which in turn, reduces the leakage current through the device. The drawback of applying a negative substrate potential V.sub.sb is that it detrimentally affects the switching speed (frequency) of the pass transistor. As a result the average time required to access the cells in the array is increased.
In recent years, complementary metal oxide semiconductor field effect transistor (CMOS) logic has seen ever increasing use in digital systems. As MOSFET technology has evolved, individual MOSFETs have become steadily smaller, e.g. with smaller feature sizes, particularly shorter channel lengths. This has allowed more and more MOSFETs to be integrated together in one integrated circuit (IC), as well as allow the requisite power supply voltage (VDD) to become smaller as well. Benefits of the former include reduced size and increased operating frequencies, while benefits of the latter include reduced power consumption. However, operating MOSFETs at today's lower power supply voltages has the undesirable effect of lowering MOSFET current which reduces the maximum operating frequency. Hence, in order to minimize reductions in circuit performance, the MOSFET threshold voltages V.sub.TH are reduced so as to minimize reductions in the MOSFET current. (Further discussion of the relationship(s) between power supply voltage, threshold voltage and operating performance for MOSFETs can be found in commonly assigned, copending U.S. patent application Ser. No. 08/292,513, filed Aug. 18, 1994, and entitled "Low Power, High Performance Junction Transistor", the disclosure of which is hereby incorporated herein by reference.) However, this in turn has the undesired effect of increasing MOSFET leakage current, i.e., MOSFET current flowing when the device is turned off.
Accordingly, building DRAM and SRAM devices using low powered and/or threshold MOS devices is problematic because the pass transistors in the devices have a tendency to leak. Leakage current in the pass transistors of DRAMs and SRAMs can cause the cells to fail. Specifically, leakage through the pass transistors accumulates onto the bit lines which prevents a sensing amplifier from sensing. Accordingly, it would be desirable to have a storage cell having pass transistors capable of operating at a low power supply voltage and/or having low threshold voltage with minimal reduction in its maximum operating frequency and reduced charge leakage.